The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

May. 29, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wei-Cheng Wu, Hsinchu, TW;

Chih-Yu Lin, Taichung, TW;

Kao-Cheng Lin, Taipei, TW;

Wei-Min Chan, New Taipei, TW;

Yen-Huei Chen, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); H01L 27/11 (2006.01); G11C 11/413 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 11/412 (2013.01); G11C 11/413 (2013.01); H01L 27/11 (2013.01);
Abstract

A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit is configured to provide the first power voltage for the plurality of first memory cells, and to provide the second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or smaller than the first power voltage and the second power voltage, for corresponding memory cells of the plurality of first memory cells and the plurality of second memory cells.


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