The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Feb. 28, 2017
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Thiago Radicchi Roque, Oakland, CA (US);

Mateus Gonçalves Silva, Belo Horizonte, BR;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 111/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 2111/02 (2020.01);
Abstract

The present disclosure relates to a computer-implemented method for performing a reset sequence simulation in an electronic design. The method may include receiving, using at least one processor, a sequence file including at least one reset, input and cycle value. The method may further include sampling during a first set of cycles set forth in the sequence file and detecting stability at a time point during a first set of cycles. The method may also include bypassing sampling during one or more remaining time points of the first set of cycles, sampling during a second set of cycles set forth in the sequence file and detecting stability at a time point during a second set of cycles.


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