The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2020
Filed:
Jun. 14, 2017
Applicant:
Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd., Zhuhai, CN;
Inventors:
Dror Hurwitz, Zhuhai, CN;
Alex Huang, Zhuhai, CN;
Assignee:
Zhuhai ACCESS Semiconductor Co., Ltd., Zhuhai, CN;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/40 (2006.01); H01L 23/00 (2006.01); H05K 1/11 (2006.01); H05K 3/00 (2006.01); H05K 3/10 (2006.01); H05K 3/26 (2006.01); H05K 3/34 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4007 (2013.01); H01L 24/17 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81805 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/01322 (2013.01); H05K 1/112 (2013.01); H05K 3/0041 (2013.01); H05K 3/108 (2013.01); H05K 3/26 (2013.01); H05K 3/3473 (2013.01); H05K 3/4647 (2013.01); H05K 2201/09436 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/025 (2013.01); H05K 2203/0278 (2013.01); H05K 2203/043 (2013.01); H05K 2203/0465 (2013.01);
Abstract
A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.