The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Mar. 31, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Stephen Thomas Palermo, Paradise Valley, AZ (US);

Dwarkadisha D. Kamhout, Jones Farm, OR (US);

Pradeepsunder Ganesh, Chandler, AZ (US);

Prabhat K. Gupta, Randolph, NJ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/26 (2006.01); H04L 29/06 (2006.01); G06F 30/34 (2020.01); G06F 30/331 (2020.01); H04L 12/24 (2006.01); H04L 29/08 (2006.01);
U.S. Cl.
CPC ...
H04L 43/16 (2013.01); G06F 30/331 (2020.01); G06F 30/34 (2020.01); H04L 43/0817 (2013.01); H04L 67/10 (2013.01); H04L 67/34 (2013.01); H04L 41/0806 (2013.01);
Abstract

Methods, apparatus, systems and articles of manufacture are disclosed to improve computing resource utilization. An example apparatus includes an application specific sensor (AS) to monitor a workload of a platform, the workload executing on at least one general purpose central processing unit (CPU) of the platform, and a dynamic deployment module (DDM) to: in response to a workload performance threshold being satisfied, identify a bit stream capable of configuring a field programmable gate array (FPGA) to execute the workload, and configure the FPGA via the bit stream to execute at least a portion of the workload.


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