The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Aug. 07, 2019
Applicants:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Remy Berthelon, Saint Martin Heres, FR;

Francois Andrieu, Saint Ismier, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 27/02 (2006.01); H01L 29/786 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7847 (2013.01); H01L 21/76283 (2013.01); H01L 21/823807 (2013.01); H01L 21/84 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 27/1203 (2013.01); H01L 29/786 (2013.01); H01L 29/7849 (2013.01);
Abstract

Longitudinal trenches extend between and on either side of first and second side-by-side strip areas. Transverse trenches extend from one edge to another edge of the first strip area to define tensilely strained semiconductor slabs in the first strip area, with the second strip area including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip area, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip area, P-channel MOS transistors are located inside and on top of the portions.


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