The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Oct. 16, 2018
Applicant:

Nustorage Technology Co., Ltd., Apia, AS (US);

Inventor:

Fu-Chou Liu, Hsin-Chu County, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11597 (2017.01); H01L 23/528 (2006.01); H01L 29/10 (2006.01); H01L 29/51 (2006.01); H01L 27/11587 (2017.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/1159 (2017.01); H01L 21/311 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11597 (2013.01); H01L 21/31144 (2013.01); H01L 23/528 (2013.01); H01L 27/1159 (2013.01); H01L 27/11587 (2013.01); H01L 29/1037 (2013.01); H01L 29/40111 (2019.08); H01L 29/516 (2013.01); H01L 29/517 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09);
Abstract

A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes a plurality of bottom source lines extending in a first horizontal direction, a stacked structure disposed on the bottom source lines, a plurality of bit lines extending in a second horizontal direction, and a plurality of pillar structures passing through the stacked structure. The stacked structure includes a plurality of composite structures spaced apart from one another and respectively located at different levels. The composite structures each include a gate conductive layer and a ferroelectric layer surrounding the gate conductive layer. Each of the pillar structures connected between the corresponding bit line and the corresponding bottom source line includes a barrier layer, a gate insulating layer, and a channel layer. The ferroelectric layer of each composite structure is insulated from the gate insulating layer of the pillar structure by the barrier layer.


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