The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Sep. 27, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kaushik Vaidyanathan, Santa Clara, CA (US);

Daniel H. Morris, San Francisco, CA (US);

Huichu Liu, Santa Clara, CA (US);

Dileep J. Kurian, Bangalore, IN;

Uygar E. Avci, Portland, OR (US);

Tanay Karnik, Portland, OR (US);

Ian A. Young, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); G06F 1/3234 (2019.01); G11C 11/413 (2006.01); G11C 14/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/2259 (2013.01); G06F 1/3275 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/413 (2013.01); G11C 14/0072 (2013.01); G11C 11/221 (2013.01);
Abstract

Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.


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