The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Jan. 12, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Dipankar Das, Pune, IN;

Roger Gramunt, Portland, OR (US);

Mikhail Smelyanskiy, Burlingame, CA (US);

Jesus Corbal, King City, OR (US);

Dheevatsa Mudigere, Bangalore, IN;

Naveen K. Mellempudi, Bangalore, IN;

Alexander F. Heinecke, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/16 (2006.01); G06F 9/30 (2018.01); G06N 3/08 (2006.01); G06N 3/063 (2006.01); G06N 3/04 (2006.01);
U.S. Cl.
CPC ...
G06N 3/084 (2013.01); G06F 9/30014 (2013.01); G06F 17/16 (2013.01); G06N 3/0445 (2013.01); G06N 3/0454 (2013.01); G06N 3/063 (2013.01);
Abstract

One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a fetch unit to fetch a single instruction having multiple input operands, wherein the multiple input operands have an unequal bit-length, a first input operand having a first bit-length and a second input operand having a second bit-length; a decode unit to decode the single instruction into a decoded instruction; an operand length unit to determine a smaller bit-length of the first bit-length and the second bit-length; and a compute unit to perform a matrix operation on the multiple input operands to generate an output value having a bit length of the smaller bit length.


Find Patent Forward Citations

Das, Dipankar. (2020). Optimized compute hardware for machine learning operations (U.S. Patent No. 10776699). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10776699

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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