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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10776292 B1

PDFFull Text
Date of Patent:
Sep. 15, 2020

Filed:

Jan. 17, 2019

Apparatus and method for protecting program memory for processing cores in a multi-core integrated circuit

Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Michael Catherwood, Georgetown, TX (US);

David Mickey, Chandler, AZ (US);

Bryan Kris, Gilbert, AZ (US);

Calum Wilkie, Chandler, AZ (US);

Jason Sachs, Chandler, AZ (US);

Andreas Reiter, Feldkirchen-Westerham, DE;

Assignee:

MICROCHIP TECHNOLOGY INCORPORATED, Chandler, AZ (US);

Attorney:

Slayden Grubert Beard PLLC

Primary Examiner:

Titus Wong

Int. Cl.
CPC ...
G06F 13/12 (2006.01); G06F 13/16 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/14 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1673 (2013.01); G06F 9/30043 (2013.01); G06F 9/3877 (2013.01); G06F 9/3879 (2013.01); G06F 12/14 (2013.01); G06F 13/4068 (2013.01); G06F 2212/1052 (2013.01);
Abstract

An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

Find Patent Forward Citations

Catherwood, Michael. (2020). Apparatus and method for protecting program memory for processing cores in a multi-core integrated circuit (U.S. Patent No. 10776292). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10776292

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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