The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Sep. 04, 2019
Applicant:

Stmicroelectronics International N.v., Plan-les-Quates, Geneva, CH;

Inventors:

Rajesh Narwal, Greater Noida, IN;

Kavindu Shekhar Benjwal, Noida, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/00 (2006.01); H03M 1/12 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1245 (2013.01); H03K 3/037 (2013.01); H03M 1/122 (2013.01); H03K 19/20 (2013.01);
Abstract

An analog-to-digital converter includes a sampling capacitor connected to a multiplexer output, discharge circuitry discharging the sampling capacitor during a first period beginning at a start of a sampling cycle, and level shifting circuitry charging the sampling capacitor to a voltage at a first analog input node modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor connected to the first analog input node and a second transistor connected to the output node, during a second period beginning at expiration of the first period. A first switch connects the first analog input node to the output node to charge the sampling capacitor to the voltage at the first analog input node, at expiration of the second period, and disconnects the first analog input node from the output node at an end of the sampling cycle of the analog-to-digital converter.


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