The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

May. 01, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Ho Jin Lee, Seoul, KR;

Seok Ho Kim, Hwaseong-si, KR;

Kwang Jin Moon, Hwaseong-si, KR;

Byung Lyul Park, Seoul, KR;

Nae In Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 21/308 (2006.01); H01L 21/3065 (2006.01); H01L 21/768 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/3065 (2013.01); H01L 21/3083 (2013.01); H01L 21/67 (2013.01); H01L 21/76898 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 24/89 (2013.01); H01L 24/92 (2013.01); H01L 25/0657 (2013.01); H01L 21/308 (2013.01); H01L 24/80 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/80357 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/80986 (2013.01); H01L 2224/81895 (2013.01); H01L 2224/81896 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06568 (2013.01);
Abstract

There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.


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