The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Jul. 20, 2018
Applicant:

Asm Ip Holding B.v., Almere, NL;

Inventors:

Yuko Kengoyama, Kawasaki, JP;

Takashi Yoshida, Fuchu, JP;

Assignee:

ASM IP Holding B.V., Almere, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05H 1/46 (2006.01); H01J 37/02 (2006.01); C23C 16/56 (2006.01); C23C 16/509 (2006.01); H01L 21/687 (2006.01); H01L 21/3065 (2006.01); H01L 21/31 (2006.01);
U.S. Cl.
CPC ...
H01J 37/026 (2013.01); C23C 16/509 (2013.01); C23C 16/56 (2013.01); H01L 21/68742 (2013.01); H01J 2237/0041 (2013.01); H01J 2237/3321 (2013.01); H01L 21/3065 (2013.01); H01L 21/31 (2013.01);
Abstract

Examples of a substrate processing method include subjecting a substrate placed on a susceptor to plasma processing, applying power to an RF electrode facing the susceptor for only a predetermined static electricity removal time to generate plasma, thereby reducing an amount of charge of the substrate, measuring a self-bias voltage of the RF electrode while susceptor pins are made to protrude from a top surface of the susceptor and lift up the substrate, and by a controller, shortening the static electricity removal time when the self-bias voltage has a positive value, and lengthening the static electricity removal time when the self-bias voltage has a negative value.


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