No-verify programming followed by short circuit test in memory device

Abstract

Techniques are described for programming memory cells without performing a verify test, where the programming is followed by a short circuit test. In one aspect, an initial programming is performed on memory cells of a first word line of a block using a program pulse with an initial magnitude, Vpgm. By reading the memory cells, Vpgm can be optimized for programming subsequent word lines. The subsequent word lines may be programmed using a no-verify program operation followed by a word line short circuit test, for one or more word lines involved in the program operation. The short circuit test can be performed concurrently on a single word line, multiple word lines and/or one or more sub-blocks of a block, based on an amount of write data which can be storage by a controller.