The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Nov. 30, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Pankaj Aggarwal, Zhudong Township, TW;

Jui-Che Tsai, Tainan, TW;

Ching-Wei Wu, Caotun Town, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 11/418 (2006.01); G11C 7/10 (2006.01); G11C 7/18 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 11/418 (2013.01); G11C 7/1045 (2013.01); G11C 7/18 (2013.01); G11C 2207/105 (2013.01); G11C 2207/108 (2013.01);
Abstract

A memory macro includes a first input terminal, a first input pin, a first memory cell array, a second memory cell array, a first set of driver circuits, a second set of driver circuits and a logic circuit. The first input pin is configured to receive a first signal indicating an operational mode of the memory macro. The first set of driver circuits is coupled to the first memory cell array. The second set of driver circuits is coupled to the second memory cell array. The logic circuit has a first terminal coupled to the first input pin and is configured to receive the first signal. The logic circuit is coupled to the first and second set of driver circuits, and is configured to generate a second signal and a third signal responsive to the first signal, and cause a change in the operational mode of the memory macro.


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