The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2020
Filed:
Sep. 25, 2017
Cadence Design Systems, Inc., San Jose, CA (US);
Nan Zhang, Andover, MA (US);
Chandrashekar Lakshminarayanan Chetput, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The present disclosure relates to a computer-implemented method for converting between a SystemVerilog user-defined net ('UDN') and an IEEE supply net is provided. The method may include providing a value conversion table ('VCT') definition associated with an electronic circuit design. The method may also include mapping, using at least one processor during a simulation, between a SystemVerilog UDN field and a IEEE supply net field. The method may further include converting at least one value between the SystemVerilog UDN field and the IEEE supply net field based upon, at least in part, the VCT definition.