The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Mar. 27, 2017
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Jalal Wehbeh, Sunnyvale, CA (US);

Harsh Vardhan, Fremont, CA (US);

Federico Politi, Menlo Park, CA (US);

Ajish Thomas, San Jose, CA (US);

Aswin Ramakrishnan, El Cerrito, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 30/39 (2020.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/367 (2020.01); G06F 30/39 (2020.01); G06F 30/398 (2020.01);
Abstract

A method for determining signal electromigration in a circuit includes selecting partitions from a netlist of the circuit is provided, each of the partitions including independent signal paths. The method includes determining a size of a partition, applying input vectors to a signal path in a large partition to obtain a signal toggle in an output, determining a current in the signal path, and identifying an electromigration result from the current flow. The method includes generating an output database for the partition, comprising an electromigration result for the first component, and combining the output database for the partition with a second output database from a second partition, the second output database including a second electromigration result for a second component in the second partition to generate an electromigration report for the netlist of the integrated circuit.


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