The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Mar. 02, 2017
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Yair Dgani, Raanana, IL;

Michael Kerner, Tel Mond M, IL;

Elan Banin, Raanana, IL;

Evgeny Shumaker, Nesher, IL;

Gil Horovitz, Ekem-Hefer, IL;

Ofir Degani, Nes-Ammin, IL;

Rotem Banin, Even-Yehuda, IL;

Aryeh Farber, Petah Tikva, IL;

Rotem Avivi, Petah-Tiqwa, IL;

Eshel Gordon, Aloney Aba, IL;

Tami Sela, Ra'anana, IL;

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G04F 7/08 (2006.01); G04F 10/00 (2006.01); H03L 7/085 (2006.01);
U.S. Cl.
CPC ...
G04F 10/005 (2013.01); H03L 7/085 (2013.01);
Abstract

A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.


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