The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Sep. 09, 2019
Applicant:

Power Integrations, Inc., San Jose, CA (US);

Inventors:

Hartley Horwitz, Ottawa, CA;

Sorin Georgescu, Gilroy, CA (US);

Kuo-Chang Robert Yang, Campbell, CA (US);

Assignee:

Power Integrations, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H03K 17/567 (2006.01); H03K 5/08 (2006.01); H01L 29/866 (2006.01); H03K 17/081 (2006.01);
U.S. Cl.
CPC ...
H03K 17/567 (2013.01); H01L 29/0619 (2013.01); H01L 29/866 (2013.01); H03K 5/08 (2013.01); H03K 17/08116 (2013.01);
Abstract

A switch having a drain, a source, and a control. The switch comprising a depletion-mode transistor including a first, a second, and a control terminal and an enhancement-mode transistor including a first, a second, and a control terminal. The first terminal of the depletion-mode transistor is the drain of the switch and the control of the depletion-mode transistor is coupled to the source of the switch. The control of the enhancement-mode transistor is coupled to the control of the switch, the second terminal of the enhancement-mode transistor is the source of the switch. The switch comprises a clamp circuit to clamp a voltage of the first terminal of the enhancement-mode transistor to a threshold, the clamp circuit comprises a resistor and a pn-junction device coupled between the first and second terminals of the enhancement-mode transistor and between the second terminal and the control of the depletion-mode transistor.


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