The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2020
Filed:
Sep. 04, 2018
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventor:
Hiroshi Yanagigawa, Ibaraki, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 21/265 (2006.01); H02H 7/18 (2006.01); H01L 29/49 (2006.01); H01L 21/308 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4236 (2013.01); H01L 21/823481 (2013.01); H01L 21/823487 (2013.01); H01L 27/088 (2013.01); H01L 29/0684 (2013.01); H01L 29/0847 (2013.01); H01L 29/41741 (2013.01); H01L 29/7827 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/26513 (2013.01); H01L 21/3081 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 29/42368 (2013.01); H01L 29/42376 (2013.01); H01L 29/4916 (2013.01); H02H 7/18 (2013.01);
Abstract
A semiconductor device which simplifies the manufacturing process while decreasing the width of separation between a first MOS transistor area and a second MOS transistor area, and a method for manufacturing the semiconductor device. A first MOS transistor and a second MOS transistor configure a bidirectional switch. The first MOS transistor and second MOS transistor each have a vertical trench structure. A first impurity region abuts on the side wall of a first gate trench of a first MOS transistor element outside the first MOS transistor area and is electrically coupled to a first source region.