The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Nov. 16, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Jaeho Jeong, Suwon-si, KR;

Sunyoung Kim, Seongnam-si, KR;

Jang-Gn Yun, Hwaseong-si, KR;

Hoosung Cho, Yongin-si, KR;

Sunghoi Hur, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/544 (2006.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/544 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 2223/5446 (2013.01);
Abstract

Three-dimensional (3D) semiconductor devices may be provided. A 3D semiconductor device may include a substrate including a chip region and a scribe line region, a cell array structure including memory cells three-dimensionally arranged on the chip region of the substrate, a stack structure disposed on the scribe line region of the substrate and including first layers and second layers that are vertically and alternately stacked, and a plurality of vertical structures extending along a vertical direction that is perpendicular to a top surface of the substrate and penetrating the stack structure.


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