The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Feb. 07, 2019
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Chenglong Zhang, Shanghai, CN;

Erhu Zheng, Shanghai, CN;

Haiyang Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 27/11521 (2017.01); H01L 21/311 (2006.01); H01L 23/535 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 23/485 (2006.01); H01L 27/11568 (2017.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76805 (2013.01); H01L 21/76819 (2013.01); H01L 23/485 (2013.01); H01L 23/535 (2013.01); H01L 27/11521 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/42324 (2013.01); H01L 29/788 (2013.01); H01L 29/792 (2013.01); H01L 21/76834 (2013.01); H01L 27/11568 (2013.01); H01L 29/4234 (2013.01);
Abstract

A semiconductor device includes a substrate structure comprising an active region, a first interlayer dielectric layer on the active region, and a first opening in the first interlayer dielectric layer and extending to the active region, at least one gate structure in the first opening and comprising spacers on sidewalls of the first opening, a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and a hardmask on the metal gate and having a first recess in a middle portion of its upper surface, the gate dielectric layer, the metal gate, and the hardmask being between the spacers, a second interlayer dielectric layer on the first dielectric layer and on at least a portion of the hardmask, and a second opening adjacent to the at least one gate structure in the first opening and exposing the spacers and a surface of the active region.


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