The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2020
Filed:
Oct. 12, 2016
Intel Corporation, Santa Clara, CA (US);
Riccardo Mariani, Pisa, IT;
Intel Corporation, Santa Clara, CA (US);
Abstract
A method for executing programs (P) in an electronic system for applications with functional safety that comprises a single-processor or multiprocessor processing system () and a further independent control module (), including: carrying out a decomposition of a program (P) that includes a safety function (SF) to be executed via said system () into a plurality of parallel subprograms (P, . . . , Pn); assigning execution of each parallel subprogram (P, . . . , Pn) to a respective processing module () of the system, in particular a processor (C, . . . , Cm) of said multiprocessor architecture () or a virtual machine (V, . . . , Vn) associated to one of said processors (C, . . . , Cm); carrying out in the system (), periodically according to a cycle frequency (f) of the program (P) during normal operation of said system (), in the context of said safety function (SF), self-test operations (A, A, A) associated to each of said subprograms (P, . . . , Pn) and to the corresponding processing modules () on which they are executed, said self-test operations (A, A, A) including: diagnostic-self-test operations (A), which carry out diagnostic self-tests; operations (A) of self-testing of system values measured on the architecture (); applicational self-test operations (A), which include operations of checking execution of conditions of use (A) and/or execution of LBISTs (Logic Built-in Self-Tests) (A), and including: generating respective self-test data (D, D, D) corresponding to the self-test operations (A, A, A) and carrying out checking operations () on said self-test data (D, D, D); exchanging said self-test data (D, D, D) continuously via a protocol (PL) of messages (MC) with the further independent control module (); carrying out at least part of said checking operations () in said further control module (); and executing said operation of decomposition of the program (P) into a plurality of parallel subprograms (P, . . . , Pn) to achieve a coverage target (A, A, A) for each of said self-test operations (A, A, A) associated to a respective subprogram (P, . . . , Pn) or processing module () in such a way that it respects a given failure-probability target (g12).
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile