The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Oct. 11, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Paul S. Diefenbaugh, Portland, OR (US);

Eugene Gorbatov, Portland, OR (US);

Andrew Henroid, Portland, OR (US);

Eric C. Samson, Folsom, CA (US);

Barnes Cooper, Hillsboro, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06F 1/3246 (2019.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3234 (2013.01); G06F 1/3246 (2013.01); G06F 1/3287 (2013.01); G06F 9/4893 (2013.01); Y02D 10/24 (2018.01); Y02D 50/20 (2018.01);
Abstract

In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.


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