The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2020

Filed:

Aug. 04, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ankush Varma, Hillsboro, OR (US);

Vasudevan Srinivasan, Hillsboro, OR (US);

Eugene Gorbatov, Hillsboro, OR (US);

Andrew D. Henroid, Portland, OR (US);

Barnes Cooper, Tigard, OR (US);

David W. Browning, Beaverton, OR (US);

Guy M. Therien, Beaverton, OR (US);

Neil W. Songer, Santa Clara, CA (US);

Krishnakanth V. Sistla, Beaverton, OR (US);

James G. Hermerding, II, Vancouver, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/26 (2006.01); G06F 1/324 (2019.01); G06F 1/20 (2006.01); G06F 1/3212 (2019.01); G06F 15/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/263 (2013.01); G06F 1/206 (2013.01); G06F 1/324 (2013.01); G06F 1/3212 (2013.01); G06F 15/00 (2013.01); Y02D 10/126 (2018.01); Y02D 10/16 (2018.01); Y02D 10/174 (2018.01);
Abstract

In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.


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