The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Dec. 24, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Albert S. Cheng, Bellevue, WA (US);

Thomas D. Lovett, Portland, OR (US);

Michael A. Parker, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/947 (2013.01); H04L 12/835 (2013.01); H04L 12/741 (2013.01); H04L 12/801 (2013.01); H04L 12/935 (2013.01); H04L 12/933 (2013.01); H04L 12/803 (2013.01);
U.S. Cl.
CPC ...
H04L 49/25 (2013.01); H04L 45/74 (2013.01); H04L 47/12 (2013.01); H04L 47/122 (2013.01); H04L 47/30 (2013.01); H04L 49/101 (2013.01); H04L 49/30 (2013.01);
Abstract

Apparatuses, methods and storage medium associated with routing data in a switch are provided. In embodiments, the switch may include route lookup circuitry determine a first set of output ports that are available to send a data packet to a destination node. The lookup circuitry may further select, based on respective congestion levels associated with the first set of output ports, a plurality of output ports for a second set of output ports from the first set of output ports. An input queue of the switch may buffer the data packet and route information associated with the second set of output ports. The switch may further include route selection circuitry to select a destination output port from the second set of output ports, based on updated congestion levels associated with the output ports of the second set of output ports. Other embodiments may be described and/or claimed.


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