The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Jul. 01, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Roee Eitan, Jerusalem, IL;

Ram Livne, Ramat Raziel, IL;

Ahmad Khairi, Hillsboro, OR (US);

Yoel Krupnik, Jerusalem, IL;

Ariel Cohen, Modiin-Makkabbim-Reut, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/38 (2006.01); H03K 5/22 (2006.01); H03K 3/037 (2006.01); H03M 1/12 (2006.01); H03K 3/356 (2006.01); H03M 1/46 (2006.01); H03M 1/40 (2006.01);
U.S. Cl.
CPC ...
H03M 1/38 (2013.01); H03K 3/037 (2013.01); H03K 3/356139 (2013.01); H03K 3/356191 (2013.01); H03K 5/22 (2013.01); H03M 1/1245 (2013.01); H03M 1/40 (2013.01); H03M 1/462 (2013.01);
Abstract

An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.


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