The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Jan. 22, 2018
Applicants:

Sumitomo Electric Industries, Ltd., Osaka-shi, JP;

Sumitomo Electric Device Innovations, Inc., Yokohama-shi, JP;

Inventors:

Toshimitsu Kaneko, Yokohama, JP;

Takuya Fujii, Yokohama, JP;

Masami Ishiura, Yokohami, JP;

Taro Hasegawa, Yokohama, JP;

Toshiyuki Taguchi, Yokohama, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01S 5/026 (2006.01); H01S 5/024 (2006.01); H01S 5/0625 (2006.01); H01S 5/125 (2006.01); H01S 5/12 (2006.01); H01S 5/343 (2006.01); H01S 5/06 (2006.01); H01S 5/227 (2006.01);
U.S. Cl.
CPC ...
H01S 5/0261 (2013.01); H01S 5/02453 (2013.01); H01S 5/06256 (2013.01); H01S 5/06258 (2013.01); H01S 5/125 (2013.01); H01S 5/1246 (2013.01); H01S 5/3434 (2013.01); H01S 5/0612 (2013.01); H01S 5/1209 (2013.01); H01S 5/2275 (2013.01); H01S 5/34306 (2013.01); H01S 5/34373 (2013.01); H01S 2304/12 (2013.01);
Abstract

A process of forming a semiconductor optical device is disclosed. The semiconductor optical device provides a waveguide structure accompanied with a heater for varying a temperature of the waveguide structure. The process includes steps of: (a) forming a striped mask on a semiconductor substrate; (b) selectively growing a dummy layer on the semiconductor substrate; (c) removing the patterned mask; (d) burying the dummy layer by a supplemental layer; (e) exposing a portion of the dummy layer by etching a portion of the supplemental layer; (f) and removing the dummy layer by immersing the dummy layer within a solution that shows an etching rate for the dummy layer enough faster than an etching rate for the supplemental layer and the substrate so as to leave a void in a region the dummy layer had existed.


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