The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Sep. 27, 2018
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Victor Moroz, Saratoga, CA (US);

Stephen Smith, Mountain View, CA (US);

Qiang Lu, Foster City, CA (US);

Assignee:

SYNOPSYS, INC., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01); H01L 29/1054 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

Roughly described, a computer program product describes a transistor with a fin, a fin support, a gate, and a gate dielectric. The fin includes a first crystalline semiconductor material which includes a channel region of the transistor between a source region of the first transistor and a drain region of the transistor. The fin is on a fin support. The fin support includes a second crystalline semiconductor material different from the first crystalline semiconductor material. The first crystalline semiconductor material of the fin and the second crystalline semiconductor material of the fin support form a first heterojunction in between. A gate, gate dielectric, and/or isolation dielectric can be positioned to improve control within the channel.


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