The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Oct. 30, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Hui-Ting Lu, Zhudong Township, TW;

Pei-Lun Wang, Zhubei, TW;

Yu-Chang Jong, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 23/495 (2006.01); H01L 29/66 (2006.01); H01L 21/761 (2006.01); H01L 29/417 (2006.01); H01L 23/485 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/761 (2013.01); H01L 23/485 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 29/402 (2013.01); H01L 29/407 (2013.01); H01L 29/4175 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/66689 (2013.01); H01L 29/78 (2013.01); H01L 29/7835 (2013.01); H01L 29/0653 (2013.01); H01L 29/0692 (2013.01); H01L 29/1045 (2013.01); H01L 29/1087 (2013.01); H01L 29/665 (2013.01);
Abstract

The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a gate structure disposed over a substrate between source and drain regions and a dielectric layer laterally extending from over the gate structure to between the gate structure and the drain region. A composite etch stop layer having a plurality of different dielectric materials is stacked over the dielectric layer. A contact etch stop layer directly contacts an upper surface and sidewalls of the composite etch stop layer. A field plate is laterally surrounded by a first inter-level dielectric (ILD) layer and vertically extends from a top of the first ILD layer, through the contact etch stop layer, and into the composite etch stop layer.


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