The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

May. 23, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Yu-Tso Lin, New Taipei, TW;

Chih-Hsien Chang, Taipei, TW;

Min-Shueh Yuan, Taipei, TW;

Robert Bogdan Staszewski, Dulin, IE;

Seyednaser Pourmousavian, Dublin, IE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01); G05F 3/02 (2006.01); H01L 27/06 (2006.01); G11C 16/30 (2006.01); H01L 29/94 (2006.01); H01L 27/07 (2006.01); H02M 3/07 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); G11C 16/30 (2013.01); H01L 27/0788 (2013.01); H01L 29/94 (2013.01); H02M 3/07 (2013.01);
Abstract

A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.


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