The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Oct. 01, 2018
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Wing Kai Chow, Austin, TX (US);

Mehmet Yildiz, Austin, TX (US);

Zhuo Li, Austin, TX (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/327 (2020.01); G06F 111/20 (2020.01); G06F 111/04 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/327 (2020.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01);
Abstract

The present disclosure relates to a system and method for routing in an electronic circuit design. Embodiments may include providing, using a processor, a hierarchical electronic design having a plurality of partitions, at least one routing blockage, a source pin location, and one or more sink pin locations. Embodiments may also include generating a routing wire network configured to connect the source pin location and the one or more sink pin locations to create one or more segments, wherein generating the routing wire network includes creating two or more feed-through ports at one or more of the plurality of partitions. Embodiments may further include applying a maze-routing approach to each of the one or more segments of the routing wire network to form a routed net associated with the hierarchical electronic design.


Find Patent Forward Citations

Chow, Wing. (2020). System and method for routing in an integrated circuit design (U.S. Patent No. 10755024). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10755024

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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