The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Mar. 31, 2016
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Naveen Muralimanohar, Palo Alto, CA (US);

Ali Shafiee Ardestani, Palo Alto, CA (US);

Ben Feinberg, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G11C 13/0002 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/7202 (2013.01); G11C 13/0007 (2013.01); G11C 2213/77 (2013.01); Y02D 10/13 (2018.01);
Abstract

In an example, a method includes receiving input data and dividing the input data into a plurality of data portions, wherein the size of each data portion is based on a significance level. The input data may be assigned to at least one resistive memory array. Assigning the input data to at least one resistive memory array may comprises at least one of (i) assigning at least one data portion of the input data to be represented by a resistive memory array representing a number of bits, wherein the number of bits represented within the resistive memory array is based on the size of the at least one data portion; and (ii) processing each data portion of the input data with at least one resistive memory array.


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