The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Nov. 04, 2019
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Sanket Naik, Bangalore, IN;

Akarsh Joshi, Bangalore, IN;

Gopal Krishna Ullal Nayak, Bangalore, IN;

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 23/66 (2006.01); H03K 23/68 (2006.01); H03K 21/02 (2006.01); H03K 21/10 (2006.01); H03L 7/197 (2006.01);
U.S. Cl.
CPC ...
H03K 23/68 (2013.01); H03K 21/026 (2013.01); H03K 21/10 (2013.01); H03K 23/66 (2013.01); H03L 7/1974 (2013.01);
Abstract

A multi-modulus frequency divider circuit includes first and second frequency division stages. The first frequency division stage receives a first input clock signal having a first oscillating frequency, a first modulus input signal, and a first division bit. The first frequency division stage divides the first oscillating frequency by a first division ratio, and generates a second input clock signal having a second oscillating frequency. The second frequency division stage receives the second input clock signal, a second modulus input signal, and a second division bit. The second frequency division stage generates an output clock signal having an output oscillating frequency by dividing the second oscillating frequency by a second division ratio.


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