The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Aug. 09, 2019
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Yan Geng, Shanghai, CN;

Jie Chen, Shanghai, CN;

Xiao Yuan Ma, Shanghai, CN;

Kai Zhu, Shanghai, CN;

Yan Ling, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356113 (2013.01);
Abstract

The present disclosure provides an IO circuit and an access control signal generation circuit for the IO circuit. In one implementation, the access control signal generation circuit includes: a bias module coupled with an IO port, for generating an access control signal according to an IO port signal and an IO control signal, where a voltage value of the access control signal is a maximum value of a voltage value of an IO port voltage division signal and a voltage value of the IO control signal, and the voltage value of the IO port voltage division signal is a percentage of a voltage value of the IO port signal; an access control module coupled with the bias module, the access control module configured to control cut-off or conduction when receiving the access control signal and the IO port signal and outputting a first interface signal; and a higher-selection module configured to generate a second interface signal according to an IO power source signal and the IO port signal. In the present disclosure, the voltage of the first interface signal varies according to the voltage of an IO port, so as to resolve the problem of reliability, thereby improving the open-drain performance.


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