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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10748915 B1

PDFFull Text
Date of Patent:
Aug. 18, 2020

Filed:

Mar. 01, 2018

Memory device and manufacturing method therefor

Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Kazuhiro Nojima, Yokkaichi Mie, JP;

Megumi Shibata, Yokkaichi Mie, JP;

Tomonori Kajino, Yokkaichi Mie, JP;

Taro Shiokawa, Yokkaichi Mie, JP;

Assignee:

TOSHIBA MEMORY CORPORATION, Tokyo, JP;

Attorney:

Foley & Lardner LLP

Primary Examiner:

Amar Movva

Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 23/535 (2006.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01); H01L 27/11575 (2017.01); G11C 29/02 (2006.01); G11C 16/04 (2006.01); H01L 27/11556 (2017.01); H01L 27/11519 (2017.01); H01L 27/11524 (2017.01); H01L 27/11565 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); G11C 29/00 (2013.01); G11C 29/025 (2013.01); G11C 29/1201 (2013.01); G11C 29/12005 (2013.01); H01L 22/14 (2013.01); H01L 22/32 (2013.01); H01L 23/535 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); G11C 16/0483 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/1206 (2013.01);
Abstract

According to one embodiment, there is provided a memory device which includes a plurality of elements that include three-dimensionally arranged memory cells, a transistor that is electrically connected to at least one of the plurality of elements, an inspection pad that is connected in series to at least one of the plurality of elements through the transistor, and a wiring that is electrically connected to the inspection pad and a gate of the transistor and capable of supplying a common potential to both the inspection pad and the transistor for turning the transistor to an OFF state.

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