The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Jan. 18, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Murshed Chowdhury, Fremont, CA (US);

Kwang-Ho Kim, Pleasanton, CA (US);

James Kai, Santa Clara, CA (US);

Johann Alsmeier, San Jose, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 15/00 (2006.01); H01L 27/06 (2006.01); H01L 27/108 (2006.01); H01L 27/11529 (2017.01); G11C 5/02 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/0688 (2013.01); G11C 5/02 (2013.01); H01L 23/481 (2013.01); H01L 24/73 (2013.01); H01L 27/10897 (2013.01); H01L 27/1157 (2013.01); H01L 27/11529 (2013.01);
Abstract

A memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, source regions located on, or in, the substrate, and at least one memory-side bonding pad electrically connected to the source regions. A logic die includes a power supply circuit configured to generate a supply voltage for the source regions, and at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures. The memory die is bonded to the logic die. The network of logic-side metal interconnect structures distributes source power from the power supply circuit over an entire area of the memory stack structures and transmits the source power to the memory die through bonded pairs of memory-side bonding pads and logic-side bonding pads.


Find Patent Forward Citations

Quick Actions:

Chowdhury, Murshed. (2020). Three-dimensional memory device containing bond pad-based power supply network for a source line and methods of making the same (U.S. Patent No. 10748894). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10748894

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…