The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10747633 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 18, 2020

Filed:

Sep. 24, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kevin Locker, Scottsdale, AZ (US);

Sai Ram Dheeraj Lokam, Chandler, AZ (US);

Siva Prasad Kota, Bangalore, IN;

Massimo Ceppi, Milan, IT;

Teo Cupaiuolo, Milan, IT;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/26 (2006.01); G01R 31/28 (2006.01); G06F 30/15 (2020.01); G06F 30/33 (2020.01); G06F 30/327 (2020.01); G01R 31/00 (2006.01); G06F 117/02 (2020.01);
U.S. Cl.
CPC ...
G06F 11/261 (2013.01); G01R 31/2846 (2013.01); G06F 30/15 (2020.01); G06F 30/327 (2020.01); G06F 30/33 (2020.01); G01R 31/007 (2013.01); G06F 2117/02 (2020.01);
Abstract

Embodiments include apparatuses, methods, and systems for testing an IC of an in-vehicle system of a CA/AD vehicle includes a storage device and processing circuitry coupled with the storage device. A gate level fault group is provided to include one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. A correlated RTL fault group is determined to be associated to a RTL circuit node, where the RTL circuit node of the RTL netlist corresponds to the gate level circuit element. Other embodiments may also be described and claimed.


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