The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Dec. 13, 2016
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, JP;

Inventors:

Rii Hirano, Tokyo, JP;

Kazunori Inoue, Kumamoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1368 (2006.01); G02F 1/1343 (2006.01); H01L 21/8236 (2006.01); H01L 27/088 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1368 (2013.01); G02F 1/134309 (2013.01); H01L 21/8236 (2013.01); H01L 27/088 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 27/1288 (2013.01); H01L 29/66742 (2013.01); H01L 29/786 (2013.01); H01L 29/7869 (2013.01); G02F 2201/123 (2013.01);
Abstract

A TFT in which a channel region is formed of an oxide semiconductor is provided. Threshold voltage shift due to holes photoexcited in the vicinity of a source electrode and a drain electrode is prevented so that reliability is enhanced. A lower semiconductor layer is partially provided between an oxide semiconductor layer and a gate insulating film. The lower semiconductor layer is present in at least one of a source overlapping region where the oxide semiconductor layer overlaps a source electrode and a drain overlapping region where the oxide semiconductor layer overlaps a drain electrode. In contrast, a region where the lower semiconductor layer is absent is provided between the source overlapping region and the drain overlapping region.


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