The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2020
Filed:
Jun. 28, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Amit Kumar Srivastava, Folsom, CA (US);
Asad Azam, Folsom, CA (US);
Jagannadha Rapeta, Folsom, CA (US);
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B60W 50/02 (2012.01); H03K 3/037 (2006.01); H03K 5/24 (2006.01); G01R 19/165 (2006.01); G01R 19/12 (2006.01); B60W 50/00 (2006.01); B60R 16/03 (2006.01);
U.S. Cl.
CPC ...
B60W 50/0205 (2013.01); B60W 50/0098 (2013.01); B60W 50/0225 (2013.01); G01R 19/12 (2013.01); G01R 19/16528 (2013.01); G01R 19/16538 (2013.01); H03K 3/037 (2013.01); H03K 5/24 (2013.01); B60R 16/03 (2013.01);
Abstract
A voltage monitoring framework is proposed to predict, report, and correct actions for performance impacting voltage droop due to power supplies in a system-on-a-chip. Both the amplitude and duration of the voltage droop are monitored. By predicting serious voltage droops early, power supplies cross check against each other to avoid catastrophic error, thus ensuring that integrated circuits making up the system-on-a-chip will maintain functional reliability.