The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2020
Filed:
Oct. 08, 2018
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 27/13 (2006.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01); H01L 29/786 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 29/94 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/5227 (2013.01); H01L 23/53295 (2013.01); H01L 24/16 (2013.01); H01L 27/13 (2013.01); H01L 28/10 (2013.01); H01L 28/60 (2013.01); H01L 29/7869 (2013.01);
Abstract
Certain aspects of the present disclosure provide a variable transistor-based capacitive element implemented on a glass or dielectric substrate. Such a variable transistor-based capacitive element may be suitable for use as a tunable capacitor in a passive-on-glass (POG) device, for example. One example device having a tunable capacitance generally includes a glass or dielectric substrate and a transistor disposed above the glass or dielectric substrate. The transistor has a gate region, a drain region, and a source region, wherein a capacitance of the transistor is configured to vary based on a voltage between the gate region and the drain region.