The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Nov. 21, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

So-young Kim, Hwaseong-si, KR;

Reum Oh, Hwaseong-si, KR;

Haesuk Lee, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); H01L 25/18 (2006.01); G11C 11/4093 (2006.01); G11C 11/4076 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/061 (2013.01); G06F 3/0673 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 11/4093 (2013.01); H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01);
Abstract

A memory die of a memory device includes a first first-in first-out (FIFO) circuit that samples data output from a memory cell array and outputs the data to a buffer die through a first through silicon via, based on a control signal transmitted from the buffer die. A buffer die of the memory device includes a second FIFO circuit that samples the data output from the first FIFO unit based on the control signal transmitted from the memory die through a second through silicon via, a calibration circuit that generates a delay code, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit, and a delay control circuit that generates the control signal transmitted to the memory die through a third through silicon via, based on the read command and the delay code.


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