The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2020
Filed:
Jan. 08, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Tarun Mahajan, Beaverton, OR (US);
Dheeraj Shetty, Bangalore, IN;
Ramnarayanan Muthukaruppan, Bangalore, IN;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/50 (2006.01); G04F 10/00 (2006.01); G05F 1/56 (2006.01); G06F 1/12 (2006.01); G06F 1/06 (2006.01); H03M 1/00 (2006.01); H03M 1/12 (2006.01); H03M 1/74 (2006.01); H03L 7/089 (2006.01); H03L 7/081 (2006.01); H03L 7/10 (2006.01);
U.S. Cl.
CPC ...
G04F 10/005 (2013.01); G05F 1/561 (2013.01); G06F 1/06 (2013.01); G06F 1/12 (2013.01); H03M 1/502 (2013.01); H03L 7/081 (2013.01); H03L 7/089 (2013.01); H03L 7/10 (2013.01); H03M 1/00 (2013.01); H03M 1/12 (2013.01); H03M 1/742 (2013.01); H03M 2201/4233 (2013.01);
Abstract
An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.