The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Feb. 15, 2019
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Robert E. Jeter, Santa Clara, CA (US);

Rakesh L. Notani, Santa Clara, CA (US);

Kai Lun Hsiung, Fremont, CA (US);

Yanzhe Liu, Sunnyvale, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/409 (2006.01); H03K 3/017 (2006.01); H03K 5/156 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1565 (2013.01); G11C 11/409 (2013.01); H03K 3/017 (2013.01);
Abstract

A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.


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