The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Aug. 26, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Khaled Ahmed, Anaheim, CA (US);

Dong Yeung Kwak, San Jose, CA (US);

Ramon C. Cancel Olmo, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); G09G 3/3233 (2016.01);
U.S. Cl.
CPC ...
H01L 29/78681 (2013.01); H01L 21/02543 (2013.01); H01L 21/02614 (2013.01); H01L 27/1225 (2013.01); H01L 29/66742 (2013.01); H01L 29/66969 (2013.01); G09G 3/3233 (2013.01); G09G 2300/0426 (2013.01); G09G 2320/0247 (2013.01);
Abstract

A display panel with reduced power consumption is described. An example of the display panel includes an array of light emitting elements that are controllable to form an image, and a Thin-Film-Transistor (TFT) backplane comprising circuitry to drive the array of light emitting elements. The TFT backplane includes a plurality of field effect transistors (FETs). Each FET includes a source electrode, a drain electrode, a channel layer contacting the source electrode and the drain electrode, and a gate electrode adjacent to the channel layer and separated from the channel layer by an insulator. The channel layer includes a layer of metal phosphide.


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