The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Mar. 15, 2019
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Cheol Soo Park, Taichung, TW;

Ming-Tang Chen, Taichung, TW;

Shuen-Hsiang Ke, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10885 (2013.01); H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 27/10891 (2013.01);
Abstract

A method of manufacturing a memory device includes following steps. A first dielectric layer is formed on the substrate between bit-line structures. First trenches are formed in the first dielectric layer. A second dielectric layer is formed to fill in the first trenches. A portion of the first dielectric layer is removed, so that a top surface of the first dielectric layer is lower than a top surface of the second dielectric layer. A first mask layer is formed to cover the top surfaces of the first and second dielectric layers. A first etching process is performed to form second trenches in the first dielectric layer. A third dielectric layer is formed to fill the second trenches. The first dielectric layer is removed to form contact openings between the second and third dielectric layers. A conductive material is formed to fill in the contact openings.


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