The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Sep. 21, 2018
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Vic Chia, Sunnyvale, CA (US);

Hong Huynh, Fremont, CA (US);

Steven A. Hanssen, San Jose, CA (US);

Robert Gregory Twiss, Chapel Hill, NC (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/40 (2006.01); F16B 5/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4006 (2013.01); F16B 5/0266 (2013.01); H01L 2023/4081 (2013.01); H01L 2023/4087 (2013.01);
Abstract

A heat sink mounting configuration is provided that is configured to prevent the heat sink from damaging ball grid arrays (BGA) of an application specific integrated circuit (ASIC) mounted on a printed circuit board (PCB) when the line card is subjected to vibrations and shocks. The heat sink mounting configuration may include a set of screws configured to be at least partially disposed within the apertures of the heat sink to secure the heat sink to the PCB. The mounting configuration includes a resilient member and a spacer disposed around the screws proximate to the apertures. The resilient members are configured to bias the heat sink against the ASIC to maintain the heat sink in contact with the ASIC. The spacers are configured to prevent the heat sink from impacting the ASIC with forces large enough to damage the BGA when the line card is subjected to vibrations and shocks.


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