The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2020
Filed:
Feb. 22, 2018
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28123 (2013.01); H01L 21/76805 (2013.01); H01L 21/76846 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01); H01L 29/41791 (2013.01); H01L 29/4983 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01);
Abstract
In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.