The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Dec. 28, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sankaran Menon, Austin, TX (US);

Krishna Kumar Ganesan, Hillsboro, OR (US);

Rolf Kuehnis, Portland, OR (US);

Eija Maarit Hillevi Manninen, Hillsboro, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/36 (2006.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 11/364 (2013.01); G06F 11/302 (2013.01); G06F 11/3428 (2013.01); G06F 11/3466 (2013.01); G06F 11/3636 (2013.01); G06F 11/3452 (2013.01); G06F 2201/865 (2013.01);
Abstract

Techniques and apparatus for error and performance analysis of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory and logic coupled to the at least one memory, wherein the logic is further to access at least one trace associated with at least one trace source, access timing information associated with the at least one trace, generate a plurality of waypoints for at least one trace, each of the plurality of waypoints comprising a step of at least one trace and a time stamp, and generate at least one performance benchmark log for the at least one trace, the at least one benchmark log comprising a plurality of benchmark waypoints corresponding to the plurality of waypoints.


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