The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2020

Filed:

Jan. 10, 2013
Applicants:

Alistair Robertson, Glasgow, GB;

Jeffrey W. Scott, Austin, TX (US);

Inventors:

Alistair Robertson, Glasgow, GB;

Jeffrey W. Scott, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30189 (2013.01); G06F 9/30123 (2013.01); G06F 9/3851 (2013.01); G06F 9/3891 (2013.01); G06F 9/462 (2013.01); G06F 9/48 (2013.01); G06F 9/50 (2013.01);
Abstract

A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units, each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers when the instruction pipeline is in the single-thread mode.


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