The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

May. 06, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Eashwar Raghuraman, Bangalore, IN;

Satish Sethuraman, Banagalore, IN;

Edward Brazil, Leixlip, IE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); H03K 17/693 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1737 (2013.01); H03K 17/693 (2013.01);
Abstract

A tristate and pass-gate based multiplexer circuit structure is described with full scan coverage capability. The circuit provides deterministic state at its output avoiding high impedance (Z) logic states in silicon. This is realized using a pull-up transistors, pull-down transistors, or through stages of combinational logic combining the multiplexer selects/enables feeding a pull-up or pull-down transistors.


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